1. Field of the Invention
The invention relates to a method of depositing a material layer and, more particularly, to a method of depositing material layers for integrated circuit fabrication.
2. Description of the Background Art
Reliably producing sub-half micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) as well as ultra large scale integration (ULSI) integrated circuits. In particular, as the fringes of circuit technology are pressed, the shrinking dimensions of interconnect features in VLSI and ULSI technology has placed additional demands on processing capabilities. For example, multilevel interconnect features require careful processing of high aspect ratio (e.g., the ratio of the feature height to the feature width) structures, such as vias, lines and contacts. Reliable formation of these features is very important to the continued effort to increase circuit density and quality of integrated circuits.
As circuit densities increase, the widths of vias, lines, and contacts may decrease to sub-micron dimensions (e.g., less than 0.25 micrometers or less), whereas the thickness of the dielectric material layers between such structures typically remains substantially constant, increasing the aspect ratios for such features. Many traditional deposition processes have difficulty filling sub-micron structures where the aspect ratio exceeds 4:1, especially where the aspect ratio exceeds 10:1.
FIGS. 1A–B illustrate the possible consequences of material layer deposition in a high aspect ratio feature 6 on a substrate 1. The high aspect ratio feature 6 may be any opening such as a space formed between adjacent features 2, a contact, a via, or a trench defined in a layer 2. As shown in FIG. 1A, a material layer 11 that is deposited using conventional deposition techniques tends to be deposited on the top edges 6T of the feature 6 at a higher rate than at the bottom 6B or sides 6S thereof creating an overhang. This overhang or excess deposition of material is sometimes referred to as crowning. Such excess material continues to build up on the top edges 6T of the feature 6, until the opening is closed off by the deposited material 11 forming a void 14 therein. Additionally, as shown in FIG. 1B, a seam 8 may be formed when a material layer 11 deposited on both sides 6S of the opening 6 merges. The presence of either voids or seams may result in unreliable integrated circuit performance.
Therefore, a need exists for a method of depositing a material layer on a substrate to provide void-free and seam-free filling of high aspect ratio openings.